Superscalar microprocessor are capable of processing multiple instructions within a common clock cycle. Pipelined microprocessors divide the processing (from dispatch to retirement) of an operation into separate pipe stages and overlap the pipestage processing of subsequent instructions in an attempt to achieve single pipestage throughput performance. Both pipelined and superscalar microprocessors are well known. Speculative execution of instructions by a microprocessor involves the microprocessor making a branch prediction of a particular program pathway given a particular branch condition. By predicting a given branch pathway, the front end of the microprocessor may process instructions while keeping the pipeline full of information before the actual branch is resolved. Provided the prediction was accurate, the microprocessor receives a large performance gain by maintaining the pipeline full of information before the branch is resolved. However, until it is known that the correct program path was taken, the information processed by the microprocessor from the branch point forward is called "speculative" information. If the checking logic of the microprocessor determines that the microprocessor mispredicted, the speculative information must be purged and the pipeline restarted at the correct program pathway.
Out-of-order processing within a microprocessor involves allowing instructions to be processed out of their program order to gain performance and increase parallelism and efficient resource usage. True data dependent instructions are not executed out-of-order, but often many instructions within a program order do not directly depend on the results of earlier instructions. These instruction may be executed (or processed) out-of-order if the microprocessor contains sufficient resources that can be used in such an efficient manner. Obviously, some instructions may not be executed out-of-order. For instance, a load from a given address must not be executed out-of-order and before an earlier store that writes to that same address. However, for other instructions that are not necessarily data or otherwise dependent, out-of-order execution allows a large performance gain over an in-order microprocessor. For a detailed explanation of speculative out-of-order execution, see M. Johnson, Superscalar Microprocessor Design, Prentice Hall, 1991. Speculative and out-of-order execution offer advantages over the prior art, including better use of resources. If multiple instructions are permitted to be executed at the same time (superscalar), this performance benefit greatly increases.
A microprocessor that is pipelined, superscalar, allows speculative execution and further allows out-of-order processing, creates a great demand on its internal resources. For that matter, any advanced microprocessor places a high demand on its internal resources. Therefore, it is advantageous to utilize the internal resources of the microprocessor as efficiently as possible. Certain conditions arise with a microprocessor that cause the instruction fetch, decode and issue portions of the microprocessor to stall (e.g., freeze the issuance of new instructions) until the stalling conditions are removed. Them are different types of stalling conditions that have different effects on the microprocessor such as a full stall and a partial stall conditions. As background, the generation of the partial stall is described in detail within a copending application assigned to the assignee of the present invention, Ser. No. 08/174,841, entitled, "Partial Width Stalls within Register Alias Table," and filed on Dec. 29, 1993. The partial stall is generated by a register alias table as a result of data dependencies between instructions accessing different widths of the same register. The present invention offers an advantageous solution to buffer resource allocation during different stalling conditions.
More specifically, advanced microprocessors, as described above, utilize a number of specialized buffers as resources to perform a number of different tasks and operations. Load and store buffers are well known resources used by microprocessors. A reservation station buffer resource may be used as a holding buffer for instructions that have been decoded and are awaiting their source data to become available so they can be executed. A reorder buffer is used to buffer results of speculative execution and provided a larger set of registers for register renaming. The present invention offers an advantageous solution to handling allocation to the above resources during various stall conditions.
Accordingly, it is an object of the present invention to increase resource use efficiency within an advanced microprocessor. It is further an object of the present invention to offer a microprocessor with beneficial allocation handling during various stall conditions. It is object of the present invention to provide different allocation techniques to buffer resources based on different stall conditions. It is further an object of the present invention to provide an allocation mechanism operable during a stall caused by buffer resource unavailability. It is another object of the present invention to provide an allocation mechanism operable during a stall caused by data dependencies between speculative instructions accessing partial register widths. These and other objects not specifically mentioned above will become clear in view of the discussions of the present invention to follow.